Nanoimprint lithography is a high throughput, low-cost lithographic technique that has demonstrated sub-10 nm feature resolution and is widely accepted as one of the potential successors to optical lithography. Currently, multi-tier nanostructures can only be achieved by using multiple lithography steps, with intermediate nanoscale alignment and overlay steps. As critical dimensions scale down with advancing technology nodes, nanoscale alignment and overlay have become increasingly more challenging. These challenges need to be addressed for nanoimprint lithography to be used for patterning high density multi-level nanoelectronic circuits.
Thus, there is a need for techniques that can enable patterning of multiple levels or tiers of nanoscale structures without employing intermediate alignment or overlay steps in order to aid continued scaling down of critical dimensions.